
LTC2220-1
11
2220_1fa
FUNCTIONAL BLOCK DIAGRA
UU
W
DIFF
REF
AMP
REF
BUF
2.2
F
1
F
0.1
F
0.1
F
1
F
INTERNAL CLOCK SIGNALS
REFH
REFL
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
RANGE
SELECT
1.6V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC+
REFHA
REFLB
REFLA REFHB
ENC–
SHIFT REGISTER
AND CORRECTION
OE
M0DE
OGND
OF
OVDD
D11
D0
CLKOUT
22201 F01
INPUT
S/H
SENSE
VCM
AIN
–
AIN
+
2.2
F
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
LVDS SHDN
+
–
+
–
+
–
+
–
VDD
GND
Figure 1. Functional Block Diagram